View source for X86-64

{{Redirect2|AMD64|Intel 64|the Intel 64-bit architecture in [[Itanium]] chips|IA-64}}
{{Use mdy dates|date=May 2014}}
{{Lowercase title}}

[[File:AMD Opteron 146 Venus, 2005.jpg|thumb|[[Opteron]], the first CPU to introduce the x86-64 extensions in 2003]]
[[File:AMD_x86-64_Architecture_Programmers_Manuals.jpg|thumb|right|The five-volume set of the ''x86-64 Architecture Programmer's Guide'', as published and distributed by AMD in 2002]]

'''x86-64''' (also known as '''x64''', '''x86_64''', '''AMD64''' and '''Intel 64'''<!--Only those mentioned in "Industry naming conventions"-->{{#tag:ref|Various names are used for the instruction set. Prior to the launch, x86-64 and x86_64 were used, while upon the release AMD named it AMD64.<ref name="inq-amd64">{{cite web
|title     = Debian AMD64 FAQ
|url       = http://wiki.debian.org/DebianAMD64Faq
|work      = Debian Wiki
|accessdate= 2012-05-03 }}</ref>
Intel initially used the names '''IA-32e''' and '''EM64T''' before finally settling on "Intel 64" for its implementation. Some in the industry, including [[Apple Inc.|Apple]],<ref name="apple-x86-64">{{cite web
|title     = x86-64 Code Model
|url       = https://developer.apple.com/library/mac/#documentation/developertools/Conceptual/MachOTopics/1-Articles/x86_64_code.html
|publisher = Apple
|accessdate= November 23, 2012}}</ref><ref name="apple-x86_64-arch-manpage">{{man|1|arch|Darwin}}</ref><ref name="apple-x86_64-email">{{cite web
  | url        = http://lists.apple.com/archives/Darwin-dev/2006/Aug/msg00095.html
  | title      = re: Intel XNU bug report
  | accessdate = 2006-10-05
  | author     = Kevin Van Vechten
  | date       = 2006-08-09
  | work       = Darwin-dev mailing list
  | publisher  = [[Apple Computer]]
  | quote      = The kernel and developer tools have standardized on "x86_64" for the name of the Mach-O architecture
}}</ref> use x86-64 and x86_64, while others, notably [[Sun Microsystems]]<ref name="solaris-x64">{{cite web
|title     = Solaris 10 on AMD Opteron
|url       = http://www.oracle.com/technetwork/server-storage/solaris/overview/solaris10amdopteron-jsp-140575.html
|publisher = Oracle
|accessdate= 2010-12-09 }}</ref>
(now [[Oracle Corporation]]) and [[Microsoft]],<ref name="ms-x64">{{cite web
|title     = Microsoft 64-Bit Computing
|url       = http://www.microsoft.com/windowsserver2008/en/us/64bit-computing.aspx
|publisher = Microsoft
|accessdate= 2010-12-09}}</ref>
use x64. The [[BSD]] family of OSs and several [[Linux distribution]]s<ref>{{cite web
|title     = AMD64 Port
|url       = http://www.debian.org/ports/amd64/
|publisher = Debian
|accessdate= November 23, 2012}}</ref><ref>{{cite web
|title     = Gentoo/AMD64 Project
|url       = http://www.gentoo.org/proj/en/base/amd64/
|publisher = Gentoo Project
|accessdate= May 27, 2013}}</ref>
use AMD64, as does Microsoft Windows internally.<ref>{{cite web|url=https://msdn.microsoft.com/en-us/library/windows/desktop/aa384274(v=vs.85).aspx|title=WOW64 Implementation Details}}</ref><ref>{{cite web|url=https://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture.aspx|title=ProcessorArchitecture Class}}</ref>
|group=note}}) is the [[64-bit]] version of the [[x86]] [[instruction set]]. It supports vastly larger amounts (theoretically, 2<sup>64</sup>&nbsp;[[byte]]s or 16&nbsp;[[exabyte]]s) of [[virtual memory]] and [[physical memory]] than is possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also provides 64-bit [[general-purpose register]]s and numerous other enhancements. x86-64 processors can boot in a fully [[backward compatible]] ''legacy mode'', without 64-bit support, for [[16-bit]] and [[32-bit]] x86 software that requires [[real mode]], or in a ''compatibility mode'' that allows 64-bit applications to coexist with 16- and 32-bit [[protected mode]] software if the 64-bit system software supports them.<ref name="amd-24593">{{cite web
  |url        = http://support.amd.com/TechDocs/24593.pdf
  |title      = Volume 2: System Programming
  |author     = AMD Corporation
  |date         = December 2016
  |work       = AMD64 Architecture Programmer's Manual
  |publisher  = AMD Corporation
  |format     = PDF
  |accessdate = 2017-03-25
  }}</ref>{{refn|group=note|In practice, 64-bit operating systems generally do not support 16-bit applications, although modern versions of Microsoft Windows contain a limited workaround that effectively supports 16-bit [[InstallShield]] and Microsoft ACME installers by silently substituting them with 32-bit code.<ref>{{cite web|url=https://blogs.msdn.microsoft.com/oldnewthing/20131031-00/?p=2783|title=If there is no 16-bit emulation layer in 64-bit Windows, how come certain 16-bit installers are allowed to run?|author=Raymond Chen |date=October 31, 2013}}</ref>}} Because the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these older [[executable]]s can run with little or no performance penalty,<ref name="x86-compat-perf">{{cite web
  |url  = ftp://ftp.software.ibm.com/software/webserver/appserv/was/64bitPerf.pdf
  |title= IBM WebSphere Application Server 64-bit Performance Demystified
  |page = 14
  |quote= "Figures 5, 6 and 7 also show the 32-bit version of WAS runs applications at full native hardware performance on the POWER and x86-64 platforms. Unlike some 64-bit processor architectures, the POWER and x86-64 hardware does not emulate 32-bit mode. Therefore applications that do not benefit from 64-bit features can run with full performance on the 32-bit version of WebSphere running on the above mentioned 64-bit platforms."
  |author    = IBM Corporation
  |date      = 2007-09-06
  |accessdate= 2010-04-09}}</ref>
while newer or recoded applications can take advantage of new features of the processor design to achieve performance improvements.

The original specification, created by [[Advanced Micro Devices|AMD]] and released in 2000, has been implemented by AMD, [[Intel Corporation|Intel]] and [[VIA Technologies|VIA]]. The [[AMD K8]] processor was the first to implement the architecture; this was the first significant addition to the [[x86]] architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modified [[NetBurst (microarchitecture)|NetBurst]] family which was fully software-compatible with AMD's design and specification. [[VIA Technologies]] introduced x86-64 in their VIA Isaiah architecture, with the [[VIA Nano]].

The x86-64 specification is distinct from the Intel [[Itanium]] architecture (formerly [[IA-64]]), which is not compatible on the native instruction set level with the x86 architecture.
{{TOC limit|3}}

== AMD64 ==
[[File:AMD64 Logo.svg|thumb|150px|right|AMD64 logo]]

=== History ===
AMD64 was created as an alternative to the radically different [[IA-64]] architecture, which was designed by Intel and [[Hewlett Packard]]. Originally announced in 1999<ref>{{cite press release
| title     = AMD Discloses New Technologies At Microporcessor Forum
| publisher = AMD
| date      = 1999-10-05
| url       = https://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx
| archiveurl = https://web.archive.org/web/20120308030806/http://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx
| archivedate = 2012-03-08
| accessdate= 2010-11-09
}}</ref> while a full specification became available in August 2000,<ref>{{cite press release
 | title     = AMD Releases x86-64 Architectural Specification; Enables Market Driven Migration to 64-Bit Computing
 | publisher = AMD
 | date      = 2000-08-10
 | url       = https://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx
 | archiveurl = https://web.archive.org/web/20120308025559/http://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx
 | archivedate = 2012-03-08
 | accessdate= 2010-11-09
}}</ref> the AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add [[64-bit computing]] capabilities to the existing x86 architecture, as opposed to Intel's approach of creating an entirely new 64-bit architecture with IA-64.

The first AMD64-based processor, the [[Opteron]], was released in April 2003.

=== Implementations ===
AMD's processors implementing the AMD64 architecture include [[Opteron]], [[Athlon 64]], [[Athlon 64 X2]], [[Athlon 64 FX]], [[Athlon II]] (followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models), [[Turion 64]], [[Turion 64 X2]], [[Sempron]] ("Palermo" E6 stepping and all "Manila" models), [[Phenom (processor)|Phenom]] (followed by "X3" or "X4" to indicate the number of cores), [[Phenom II]] (followed by "X2", "X3", "X4" or "X6" to indicate the number of cores), [[List of AMD FX microprocessors|FX]], [[AMD Accelerated Processing Unit|Fusion/APU]] and [[Ryzen]]/[[Epyc]].

=== Architectural features ===
The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose [[processor register]]s (for example, rax and rbx), 64-bit [[Integer (computer science)|integer]] arithmetic and logical operations, and 64-bit [[Protected Virtual Address Mode|virtual addresses]]. The designers took the opportunity to make other improvements as well. Some of the most significant changes are described below.

; 64-bit integer capability
: All [[general-purpose register]]s (GPRs) are expanded from 32&nbsp;[[bit]]s to 64&nbsp;bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., can now operate directly on 64-bit integers. [[Stack (data structure)|Pushes and pops]] on the [[Stack register|stack]] default to 8-byte strides, and [[pointer (computer programming)|pointers]] are 8 bytes wide.
; Additional registers
: In addition to increasing the size of the general-purpose registers, the number of named general-purpose registers is increased from eight (i.e. eax, ecx, edx, ebx, esp, ebp, esi, edi) in x86 to 16 (i.e. rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15). It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent.
: AMD64 still has fewer registers than many common [[RISC]] [[instruction set]]s (which typically have 32&nbsp;registers{{citation needed|date=November 2016}}) or [[VLIW]]-like machines such as the [[IA-64]] (which has 128&nbsp;registers). However, an AMD64 implementation may have far more internal registers than the number of architectural registers exposed by the instruction set (see [[register renaming]]).
; Additional XMM (SSE) registers
: Similarly, the number of 128-bit XMM<!-- don't confuse this name with MMX; MMX has no hardware registers and is mapped to the FPU stack. Here we talk about SSE (XMM) registers --> registers (used for [[Streaming SIMD Extensions|Streaming SIMD]] instructions) is also increased from 8 to 16.
; Larger virtual address space
: The AMD64 architecture defines a 64-bit virtual address format, of which the low-order 48 bits are used in current implementations.<ref name="amd-24593"/>{{rp|page=120|date=November 2012}} This allows up to 256&nbsp;[[Terabyte|TB]] (2<sup>48</sup> [[byte]]s) of virtual address space. The architecture definition allows this limit to be raised in future implementations to the full 64 bits,<ref name="amd-24593"/>{{rp|page=2|date=November 2012}}{{rp|page=3|date=November 2012}}{{rp|page=13|date=November 2012}}{{rp|page=117|date=November 2012}}{{rp|page=120|date=November 2012}} extending the virtual address space to 16&nbsp;[[Exabyte|EB]] (2<sup>64</sup> bytes). This is compared to just 4&nbsp;[[Gigabyte|GB]] (2<sup>32</sup> bytes) for the x86.<ref name="intel-253668">{{cite web
  |url       = http://www.intel.com/Assets/PDF/manual/253668.pdf
  |title     = Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part&nbsp;1
  |accessdate= 2010-05-29
  |format    = PDF
  |pages     = 4–10}}</ref>
: This means that very large files can be operated on by [[Memory-mapped file|mapping]] the entire file into the process' address space (which is often much faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.
; Larger physical address space
: The original implementation of the AMD64 architecture implemented 40-bit [[physical address]]es and so could address up to 1&nbsp;TB (2<sup>40</sup> bytes) of RAM.<ref name="amd-24593"/>{{rp|page=24|date=November 2012}} Current implementations of the AMD64 architecture (starting from [[AMD K10|AMD 10h microarchitecture]]) <!--- it's "10h", as in 10 hex, not 10th as in tenth. Please see the reference named amd10h, immediately following. Please do not change this back to "10th" ---> extend this to 48-bit physical addresses<ref name="amd10h">{{cite web|url=http://developer.amd.com/wordpress/media/2012/10/31116.pdf |title=BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h Processors |accessdate=2016-02-27 |format=PDF |page=24 |quote=Physical address space increased to 48 bits.}}</ref> and therefore can address up to 256&nbsp;TB of RAM. The architecture permits extending this to 52 bits in the future<ref name="amd-24593"/>{{rp|page=24|date=November 2012}}<ref>
{{cite web
  |url      = http://www.amd64.org/fileadmin/user_upload/pub/64bit_Linux-Myths_and_Facts.pdf
  |title      = Myth and facts about 64-bit Linux
  |accessdate      = 2010-05-30
  |date      = 2008-03-02
  |format      = PDF
  |page      = 7
  |quote      = Physical address space increased to 48 bits
  |deadurl      = yes
  |archiveurl      = https://web.archive.org/web/20101010233951/http://www.amd64.org/fileadmin/user_upload/pub/64bit_Linux-Myths_and_Facts.pdf
  |archivedate      = October 10, 2010
  |df      = mdy-all
  }}</ref> (limited by the page table entry format);<ref name="amd-24593"/>{{rp|page=131|date=November 2012}} this would allow addressing of up to 4&nbsp;[[Petabyte|PB]] of RAM. For comparison, 32-bit x86 processors are limited to 64&nbsp;GB of RAM in [[Physical Address Extension]] (PAE) mode,<ref name="shanley-ppro">{{cite book
  |title    = Pentium Pro and Pentium II System Architecture
  |edition  = Second
  |last     = Shanley
  |first    = Tom
  |isbn     = 0-201-30973-4
  |series   = PC System Architecture Series
  |year     = 1998
  |publisher= Addison-Wesley
  |page     = 445}}</ref> or 4&nbsp;GB of RAM without PAE mode.<ref name="amd-24593"/>{{rp|page=4|date=November 2012}}
; Larger physical address space in legacy mode
: When operating in [[legacy mode]] the AMD64 architecture supports [[Physical Address Extension]] (PAE) mode, as do most current x86 processors, but AMD64 extends PAE from 36 bits to an architectural limit of 52&nbsp;bits of physical address. Any implementation therefore allows the same physical address limit as under long mode.<ref name="amd-24593"/>{{rp|page=24|date=November 2012}}
; Instruction pointer relative data access
: Instructions can now reference data relative to the instruction pointer (RIP register). This makes [[position independent code]], as is often used in [[Library (computing)#Shared libraries|shared libraries]] and code loaded at run time, more efficient.
; SSE instructions
: The original AMD64 architecture adopted Intel's [[Streaming SIMD Extensions|SSE]] and [[SSE2]] as core instructions. These instruction sets provide a vector supplement to the scalar [[x87]] FPU, for the single-precision and double-precision data types. SSE2 also offers integer vector operations, for data types ranging from 8bit to 64bit precision. This makes the vector capabilities of the architecture on par with those of the most advanced x86 processors of its time. These instructions can also be used in 32-bit mode. The proliferation of 64-bit processors has made these vector capabilities ubiquitous in home computers, allowing the improvement of the standards of 32-bit applications. The 32-bit edition of Windows 8, for example, requires the presence of SSE2 instructions.<ref>{{cite web|last=Microsoft Corporation|title=What is PAE, NX, and SSE2 and why does my PC need to support them to run Windows 8 ?|url=http://windows.microsoft.com/en-GB/windows-8/what-is-pae-nx-sse2|accessdate=19 March 2013}}</ref> [[SSE3]] instructions and later [[Streaming SIMD Extensions]] instruction sets are not standard features of the architecture.
; No-Execute bit
: The No-Execute bit or [[NX bit]] (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "[[Buffer overflow|buffer overrun]]" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the [[80286]] as an attribute of [[segment descriptor]]s; however, this works only on an entire segment at a time.
:[[x86 memory segmentation|Segmented addressing]] has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of zero and (in their 32 bit implementation) a size of 4&nbsp;GB. AMD was the first x86-family vendor to implement no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.
; Removal of older features
: A few "system programming" features of the x86 architecture were either unused or underused in modern operating systems and are either not available on AMD64 in long (64-bit and compatibility) mode, or exist only in limited form. These include segmented addressing (although the FS and GS segments are retained in vestigial form for use as extra base pointers to operating system structures),<ref name="amd-24593"/>{{rp|page=70|date=November 2012}} the [[Task State Segment|task state switch]] mechanism, and [[virtual 8086 mode]]. These features remain fully implemented in "legacy mode", allowing these processors to run 32-bit and 16-bit operating systems without modifications. Some instructions that proved to be rarely useful are not supported in 64-bit mode, including saving/restoring of segment registers on the stack, saving/restoring of all registers (PUSHA/POPA), decimal arithmetic, BOUND and INTO instructions, and "far" jumps and calls with immediate operands.

=== {{Anchor|VIRTUAL-ADDRESS-SPACE}}Virtual address space details ===

==== Canonical form addresses ====
{{Multiple image
 | header    = Canonical address space implementations (diagrams not to scale)
 | width     = 150
 | direction = horizontal
 | align     = right
 | image1    = AMD64-canonical--48-bit.svg
 | caption1  = Current 48-bit implementation
 | image2    = AMD64-canonical--56-bit.svg
 | caption2  = 56-bit implementation
 | image3    = AMD64-canonical--64-bit.svg
 | caption3  = 64-bit implementation
}}

Although virtual addresses are 64&nbsp;bits wide in 64-bit mode, current implementations (and all chips known to be in the planning stages) do not allow the entire virtual address space of 2<sup>64</sup> bytes (16&nbsp;EB) to be used.
This would be approximately four billion times the size of virtual address space on 32-bit machines. Most operating systems and applications will not need such a large address space for the foreseeable future, so implementing such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD therefore decided that, in the first implementations of the architecture, only the least significant 48&nbsp;bits of a virtual address would actually be used in address translation ([[page table]] lookup).<ref name="amd-24593" />{{rp|page=120|date=November 2012}}

In addition, the AMD specification requires that the most significant 16 bits of any virtual address,  bits 48 through 63, must be copies of bit 47 (in a manner akin to [[sign extension]]). If this requirement is not met, the processor will raise an exception.<ref name="amd-24593" />{{rp|page=131|date=November 2012}} Addresses complying with this rule are referred to as "canonical form."<ref name="amd-24593" />{{rp|page=130|date=November 2012}} Canonical form addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through FFFFFFFF'FFFFFFFF, for a total of 256&nbsp;TB of usable virtual address space. This is still 65,536 times larger than the virtual 4 GB address space of 32-bit machines.

This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to, the [[Windows NT]] family) take the higher-addressed half of the address space (named [[kernel space]]) for themselves and leave the lower-addressed half ([[user space]]) for application code, user mode stacks, heaps, and other data regions.<ref name="win-lim-msdn" /> The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits prevents their use by the operating system in [[tagged pointer]]s as flags, privilege markers, etc., as such use could become problematic when the architecture is extended to implement more virtual address bits.

The first versions of Windows for x64 did not even use the full 256&nbsp;TB; they were restricted to just 8&nbsp;TB of user space and 8&nbsp;TB of kernel space.<ref name="win-lim-msdn">{{cite web|url=http://msdn.microsoft.com/en-us/library/windows/desktop/aa366778(v=vs.85).aspx#memory_limits |title=Memory Limits for Windows Releases |website=[[MSDN]] |publisher=[[Microsoft]] |date=November 16, 2013 |accessdate=January 20, 2014}}</ref> Windows did not support the entire 48-bit address space until [[Windows&nbsp;8.1]], which was released in October 2013.<ref name="win-lim-msdn" /> <!--- it would be good to include other OS's limits here. --->

==== Page table structure ====
The 64-bit addressing mode ("[[long mode]]") is a superset of [[Physical Address Extension]]s (PAE); because of this, [[paging|page]] sizes may be 4&nbsp;[[Kilobyte|KB]] (2<sup>12</sup> bytes) or 2&nbsp;[[Megabyte|MB]] (2<sup>21</sup> bytes).<ref name="amd-24593"/>{{rp|page=120|date=November 2012}} Long mode also supports page sizes of 1&nbsp;[[Gigabyte|GB]] (2<sup>30</sup> bytes).<ref name="amd-24593"/>{{rp|page=120|date=November 2012}} Rather than the three-level [[page table]] system used by systems in PAE mode, systems running in [[long mode]] use four levels of page table: PAE's ''Page-Directory Pointer Table'' is extended from 4 entries to 512, and an additional ''Page-Map Level&nbsp;4 (PML4) Table'' is added, containing 512 entries in 48-bit implementations.<ref name="amd-24593"/>{{rp|page=131|date=November 2012}} In implementations providing larger virtual addresses, this latter table would either grow to accommodate sufficient entries to describe the entire address range, up to a theoretical maximum of 33,554,432 entries for a 64-bit implementation, or be over ranked by a new mapping level, such as a PML5. A full mapping hierarchy of 4&nbsp;KB pages for the whole 48-bit space would take a bit more than 512&nbsp;GB of RAM (about 0.195% of the 256&nbsp;TB virtual space).

==== Operating system limits ====
The operating system can also limit the virtual address space. Details, where applicable, are given in the "[[X86-64#Operating system compatibility and characteristics|Operating system compatibility and characteristics]]" section.

=== Physical address space details ===
Current AMD64 processors support a physical address space of up to 2<sup>48</sup> bytes of RAM, or 256&nbsp;TB.<ref name="amd10h"/> However, {{as of|2010|06|lc=1}}, there were no known x86-64 [[motherboard]]s that support 256&nbsp;TB of RAM.<ref>{{cite web
|url       = http://www.supermicro.com/Aplus/motherboard/Opteron6100/
|title     = Opteron 6100 Series Motherboards
|publisher = Supermicro Corporation
|accessdate= 2010-06-22}}</ref><ref>{{cite web
|url       = http://www.supermicro.com/products/motherboard/Xeon1333/#1366
|title     = Supermicro Xeon<!-- AutoEd: rm unicode ctrl char w/no win-1252 mapping, intent unknown -->Solutions
|publisher = Supermicro Corporation
|accessdate= 2010-06-20}}</ref><ref>{{cite web
|url       = http://www.supermicro.com/Aplus/motherboard/Opteron8000/
|title     = Opteron 8000 Series Motherboards
|publisher = Supermicro Corporation
|accessdate= 2010-06-20}}</ref><ref>{{cite web
|url       = http://www.supermicro.com/products/motherboard/Core/index.cfm#1366
|title     = Tyan Product Matrix
|publisher = MiTEC International Corporation
|accessdate= 2010-06-21}}</ref>{{failed verification|date=May 2016}}
The operating system may place additional limits on the amount of RAM that is usable or supported. Details on this point are given in the "[[X86-64#Operating system compatibility and characteristics|Operating system compatibility and characteristics]]" section of this article.

=== {{Anchor|OPMODES}}Operating modes ===
{| class="wikitable" style="text-align: center;"
|-
! Operating mode
! Operating sub-mode
! [[Operating system]] required
! Type of code being run
! Default address size
! Default operand size
! Supported typical operand sizes
! [[Register file]] size
! Typical [[General Purpose Register|GPR]] width
|-
| rowspan="3"| [[Long mode]]
| 64-bit mode
| 64-bit operating system or boot loader
| [[Long mode|64-bit code]]
| 64 bits
| 32 bits
| 8, 16, 32, or 64 bits
| 16 registers per file
| 64 bits
|-
| rowspan="2"| Compatibility mode
| 64-bit operating system or boot loader
| [[Protected mode#The 386|32-bit protected mode code]]
| 32 bits
| 32 bits
| 8, 16, or 32 bits
| 8 registers per file
| 32 bits
|-
| 64-bit operating system
| [[Protected mode#The 286|16-bit protected mode code]]
| 16 bits
| 16 bits
| 8, 16, or 32 bits
| 8 registers per file
| 32 bits
|-
| rowspan="4"| Legacy mode
| rowspan="2"| [[Protected mode]]
| 32-bit operating system or boot loader, or 64-bit boot loader
| [[Protected mode#The 386|32-bit protected mode code]]
| 32 bits
| 32 bits
| 8, 16, or 32 bits
| 8 registers per file
| 32 bits
|-
| 16-bit protected mode operating system or boot loader, or 32- or 64-bit boot loader
| [[Protected mode#The 286|16-bit protected mode code]]
| 16 bits
| 16 bits
| 8, 16, or 32 bits
| 8 registers per file
| 16 or 32 bits
|-
| [[Virtual 8086 mode]]
| 16- or 32-bit protected mode operating system
| [[Real mode|16-bit real mode code]]
| 16 bits
| 16 bits
| 8, 16, or 32 bits
| 8 registers per file
| 16 or 32 bits
|-
| [[Real mode]]
| 16-bit real mode operating system or boot loader, or 32- or 64-bit boot loader
| [[Real mode|16-bit real mode code]]
| 16 bits
| 16 bits
| 8, 16, or 32 bits
| 8 registers per file
| 16 or 32 bits
|}

The traditional x87 FPU register stack is not included in the register file size extension in 64-bit mode, compared with the XMM registers used by SSE2, which did get extended. The [[x87]] register stack is not a simple register file although it does allow direct access to individual registers by low cost exchange operations. Also note that 16-bit code written for the 80286 and below cannot use the 32-bit general-purpose registers ([[General Purpose Register|GPRs]]). 16-bit code written for the 80386 and above can use 32-bit GPRs, but defaults to using 16-bit operands.

[[File:AMD64StateDiagram.svg|thumb|400px|State diagram of the x86-64 operating modes]]

The architecture has two primary modes of operation, long mode and legacy mode.

==== Long mode ====
{{main article|Long mode}}

Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software.<ref name="amd-24593"/>{{rp|11}} However, such programs may be started from an operating system running in long mode on processors supporting [[VT-x]] or [[AMD-V]] by creating a virtual processor running in the desired mode.

Since the basic [[instruction set]] is the same, there is almost no performance penalty for executing protected mode x86 code. This is unlike Intel's [[IA-64]], where differences in the underlying instruction set means that running 32-bit code must be done either in emulation of x86 (making the process slower) or with a dedicated x86 coprocessor. However, on the x86-64 platform, many x86 applications could benefit from a 64-bit [[recompile]], due to the additional registers in 64-bit code and guaranteed SSE2-based FPU support, which a [[compiler]] can use for optimization. However, applications that regularly handle integers wider than 32 bits, such as cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to take advantage of the 64-bit registers.

==== Legacy mode ====
Legacy mode is the mode used by 16-bit ("protected mode" or "real mode") and 32-bit operating systems. In this mode, the processor acts like a 32-bit x86 processor, and only 16-bit and 32-bit code can be executed. Legacy mode allows for a maximum of 32&nbsp;bit virtual addressing which limits the virtual address space to 4&nbsp;GB.<ref name="amd-24593"/>{{rp|page=14|date=November 2012}}{{rp|page=24|date=November 2012}}{{rp|page=118|date=November 2012}} 64-bit programs cannot be run from legacy mode.

== Intel 64 ==
'''Intel&nbsp;64''' is Intel's implementation of x86-64, used and implemented in various processors made by Intel.

=== History ===
Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of adopting the [[instruction set architecture|ISA]] which AMD had created as an extension to Intel's own x86 processor line.

Intel's project was originally [[codename]]d ''Yamhill'' (after the [[Yamhill River]] in Oregon's Willamette Valley).{{cn|date=August 2017}} After several years of denying its existence, Intel announced at the February 2004 [[Intel Developer Forum|IDF]] that the project was indeed underway. Intel's chairman at the time, [[Craig Barrett (chief executive)|Craig Barrett]], admitted that this was one of their worst-kept secrets.<ref>{{cite web |url=https://www.theinquirer.net/inquirer/news/1042795/craig-barrett-confirms-bit-address-extensions-xeon-and-prescott |title=Craig Barrett confirms 64 bit address extensions for Xeon. And Prescott. |publisher=The Inquirer |date=2004-02-17}}</ref><ref>[http://www.internetnews.com/ent-news/article.php/3518781 "A Roundup of 64-Bit Computing", from internetnews.com]</ref>

Intel's name for this instruction set has changed several times. The name used at the IDF was ''CT'' (presumably{{or|date=August 2017}} for ''Clackamas Technology'', another codename from an [[Clackamas River|Oregon river]]); within weeks they began referring to it as ''IA-32e'' (for [[IA-32]] extensions) and in March 2004 unveiled the "official" name ''EM64T'' (Extended Memory 64 Technology). In late 2006 Intel began instead using the name ''Intel&nbsp;64'' for its implementation, paralleling AMD's use of the name AMD64.<ref>{{cite web
| url        = http://www.intel.com/technology/intel64/index.htm
| title      = Intel&nbsp;64 Architecture
| accessdate = 2007-06-29
| publisher  = [[Intel]]
}}</ref>

The first processor to implement Intel&nbsp;64 was the multi-socket processor [[Xeon]] code-named ''[[Xeon#Nocona and Irwindale|Nocona]]'' in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel&nbsp;64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the [[NX bit]]) to Intel&nbsp;64, and has been included in then current Xeon code-named ''Irwindale''. Intel's official launch of Intel&nbsp;64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M.

The first Intel [[mobile processor]] implementing Intel&nbsp;64 is the [[Merom (microprocessor)|Merom]] version of the [[Core 2]] processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs ([[Core Duo]], [[Pentium M]], [[Celeron M]], [[Pentium 4|Mobile Pentium 4]]) implement Intel&nbsp;64.

The Intel white paper "5-Level Paging and 5-Level EPT" describe a mechanism, under development by Intel, that will allow Intel 64 processors to support 57-bit virtual addresses, with an additional page table level.<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf|title=5-Level Paging and 5-Level EPT|publisher=Intel|date=May 2017|accessdate=June 17, 2017}}</ref>

=== Implementations ===
Intel's processors implementing the Intel64 architecture include the [[Pentium 4]] F-series/5x1 series, 506, and 516, [[Celeron D]] models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later [[Celeron]]s, all models of [[Xeon]] since "[[Xeon#Nocona and Irwindale|Nocona]]", all models of [[Pentium Dual-Core]] processors since "[[Merom (microprocessor)#Merom-2M|Merom-2M]]", the [[Intel Atom|Atom]] 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, and all versions of the [[Pentium D]], [[Pentium Extreme Edition]], [[Core&nbsp;2]], [[Intel Core i7|Core&nbsp;i7]], [[Intel Core i5|Core&nbsp;i5]], and [[Core&nbsp;i3]] processors.

== VIA's x86-64 implementation ==
[[VIA Technologies]] introduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division, [[Centaur Technology]].<ref>{{cite web
|title      = VIA to launch new processor architecture in 1Q08
|publisher  = [[DigiTimes]]
|url        = http://www.digitimes.com/news/a20070725PD206.html
|accessdate = 2007-07-25
|format     = subscription required}}</ref>
Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008,<ref>{{cite web
|title      = Isaiah revealed: VIA's new low-power architecture
|publisher  = Ars Technica
|url        = https://arstechnica.com/articles/paedia/cpu/via-cpu-isaiah.ars
|accessdate = 2008-01-24
|first      = Jon
|last       = Stokes
|date       = 2008-01-23}}</ref> and launched on May 29 under the [[VIA Nano]] brand name.<ref>{{cite press release
|title      = VIA Launches VIA Nano Processor Family
|publisher  = [[VIA Technologies|VIA]]
|url        = http://www.viatech.com/en/2008/05/via-launches-via-nano-processor-family/
|accessdate = 2017-05-25
|date       = 2008-05-29}}</ref>

The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.
It is expected that the Isaiah architecture will be twice as fast in integer performance and four times as fast in [[floating-point]] performance as the previous-generation [[VIA Esther]] at an equivalent [[clock speed]]. Power consumption is also expected to be on par with the previous-generation VIA CPUs, with [[thermal design power]] ranging from 5&nbsp;W to 25&nbsp;W.<ref>{{cite web
|publisher = [[VIA Technologies|VIA]]
|url       = http://www.via.com.tw/en/downloads/presentations/processors/pb_via-isaiah_080124.pdf
|title     = VIA Isaiah Architecture Introduction
|format    = PDF
|accessdate= 2013-07-31
|date      = 2008-01-23}}</ref>
Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and [[x86 virtualization]] which were unavailable on its predecessors, the [[VIA C7]] line, while retaining their encryption extensions.

== Differences between AMD64 and Intel 64 ==
Although nearly identical, there are some differences between the two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used for [[system programming]].<ref name=trcscott>{{cite web |last= Wasson |first= Scott |title= 64-bit computing in theory and practice |url= http://techreport.com/articles.x/8131/1 |work= The Tech Report |publisher= The Tech Report |accessdate= 2011-03-22}}</ref> Compilers generally produce [[executable]]s (i.e. [[machine code]]) that avoid any differences, at least for ordinary [[application software|application programs]]. This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions.

=== Recent implementations ===
* Intel&nbsp;64's [[find first set|<code>BSF</code>]] and [[find first set|<code>BSR</code>]] instructions act differently than AMD64's when the source is zero and the operand size is 32&nbsp;bits. The processor sets the zero flag and leaves the upper 32&nbsp;bits of the destination undefined.
* AMD64 requires a different microcode update format and control MSRs (model-specific registers) while Intel&nbsp;64 implements [[microcode]] update unchanged from their 32-bit only processors.
* Intel&nbsp;64 lacks some MSRs that are considered architectural in AMD64. These include <code>SYSCFG</code>, <code>TOP_MEM</code>, and <code>TOP_MEM2</code>.
* Intel&nbsp;64 allows <code>SYSCALL</code>/<code>SYSRET</code> only in 64-bit mode (not in compatibility mode),<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z|pages=4–397|publisher=Intel|date=September 2013|accessdate=2014-01-21}}</ref> and allows <code>SYSENTER</code>/<code>SYSEXIT</code> in both modes.<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z|pages=4–400|publisher=Intel|date=September 2013|accessdate=2014-01-21}}</ref> AMD64 lacks <code>SYSENTER</code>/<code>SYSEXIT</code> in both sub-modes of [[long mode]].<ref name="amd-24593"/>{{rp|33}}
* In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel&nbsp;64 ignores this prefix: the instruction has 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses 16-bit offset field in the instruction, and clears the top 48&nbsp;bits of instruction pointer.
* AMD processors raise a floating point Invalid Exception when performing an <code>FLD</code> or <code>FSTP</code> of an 80-bit signalling NaN, while Intel processors do not.
* Intel&nbsp;64 lacks the ability to save and restore a reduced (and thus faster) version of the [[floating-point]] state (involving the <code>FXSAVE</code> and <code>FXRSTOR</code> instructions).
* AMD processors ever since [[Opteron]] Rev. E and [[Athlon 64]] Rev. D have reintroduced limited support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to ease [[x86 virtualization#64-bit|virtualization]] of 64-bit guests.<ref>{{cite web |url= http://www.pagetable.com/?p=25 |title= How retiring segmentation in AMD64 long mode broke VMware |publisher= Pagetable.com |date= 2006-11-09 |accessdate= 2010-05-02}}</ref><ref>{{cite web |url= http://download3.vmware.com/vmworld/2005/pac346.pdf |title= VMware and CPU Virtualization Technology |format= PDF |publisher= VMWare |date= |accessdate= 2010-09-08}}</ref>
* When returning to a non-canonical address using <code>SYSRET</code>, AMD64 processors execute the general protection fault handler in privilege level 3, while on Intel&nbsp;64 processors it is executed in privilege level 0.<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z|pages=4–412|publisher=Intel|date=September 2014|accessdate=2014-12-28}}</ref><ref>{{cite web|url=http://support.amd.com/TechDocs/24594.pdff|title=AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions|page=417|publisher=AMD|date=December 2016|accessdate=2017-03-25}}</ref>

=== Older implementations ===
* Early AMD64 processors (typically on Socket 939 and 940) lacked the <tt>CMPXCHG16B</tt> instruction, which is an extension of the <tt>CMPXCHG8B</tt> instruction present on most post-[[80486]] processors. Similar to <tt>CMPXCHG8B</tt>, <tt>CMPXCHG16B</tt> allows for [[atomic operation]]s on octal words. This is useful for parallel algorithms that use [[compare and swap]] on data larger than the size of a pointer, common in [[lock-free and wait-free algorithms]]. Without <tt>CMPXCHG16B</tt> one must use workarounds, such as a [[critical section]] or alternative lock-free approaches.<ref>{{cite web|url=http://www.research.ibm.com/people/m/michael/disc-2004.pdf|title=Practical Lock-Free and Wait-Free LL/SC/VL Implementations Using 64-Bit CAS|author=Maged M. Michael|publisher=IBM|accessdate=2014-01-21}}</ref> Its absence also prevents 64-bit [[Microsoft Windows|Windows]] prior to Windows 8.1 from having a [[user-mode]] address space larger than 8&nbsp;terabytes.<ref>{{cite web|url=https://blogs.msdn.microsoft.com/oldnewthing/20040817-00/?p=38153#comment-204583|title=Why is the virtual address space 4GB anyway?|website=The Old New Thing|author=darwou|date=August 20, 2004|publisher=Microsoft}}</ref> The 64-bit version of Windows 8.1 requires the instruction.<ref  name="CPUinsts8.1">{{cite web
|url=http://windows.microsoft.com/en-us/windows-8/system-requirements
|title=System Requirements—Windows 8.1
|quote=To install a 64-bit OS on a 64-bit PC, your processor needs to support CMPXCHG16b, PrefetchW, and LAHF/SAHF.
|accessdate=2014-04-27
}}</ref>
* Early AMD64 and Intel&nbsp;64 CPUs lacked <tt>LAHF</tt> and <tt>SAHF</tt> instructions in 64-bit mode. AMD introduced these instructions (also in 64-bit mode) with their Athlon&nbsp;64, Opteron and Turion&nbsp;64 revision&nbsp;D processors in March 2005<ref>[http://support.amd.com/us/Processor_TechDocs/25759.pdf "Revision Guide for AMD Athlon&nbsp;64 and AMD Opteron Processors", from AMD]</ref><ref>[http://www.theinquirer.net/inquirer/news/1021373/amd-turion-64-pictured-up-and-running "AMD Turion&nbsp;64 pictured up and running", from The Inquirer]</ref><ref>[http://www.theinquirer.net/inquirer/news/1042931/athlon-64-revision-e-wont-work-on-some-nforce-34--boards "Athlon&nbsp;64 revision&nbsp;E won't work on some Nforce 3/4 boards", from The Inquirer]</ref> while Intel introduced the instructions with the Pentium&nbsp;4&nbsp;G1 stepping in December 2005. The 64-bit version of Windows 8.1 requires this feature.<ref name="CPUinsts8.1"/>
* Early Intel CPUs with Intel&nbsp;64 also lack the [[NX bit]] of the AMD64 architecture. This feature is required by all versions of Windows 8.x.
* Early Intel&nbsp;64 implementations ([[Pentium 4#Prescott|Prescott]] and [[Pentium 4#Cedar Mill|Cedar Mill]]) only allowed access to 64&nbsp;GB of physical memory while original AMD64 implementations allowed access to 1&nbsp;TB of physical memory. Recent AMD64 implementations provide 256&nbsp;TB of physical address space (and AMD plans an expansion to 4&nbsp;PB),{{Citation needed|date=October 2010}} while some Intel&nbsp;64 implementations could address up to 64&nbsp;TB.<ref>"Intel 64 architecture increases the linear address space for software to 64 bits and supports physical address space up to 46 bits." on page Vol. 1 2-21 of [http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-manual-325462.html Intel 64 and IA-32 Architectures Software Developer’s Manual September 2014]</ref> Physical memory capacities of this size are appropriate for large-scale applications (such as large databases), and high-performance computing (centrally oriented applications and scientific computing).

== Adoption ==
[[File:Processor families in TOP500 supercomputers.svg|thumb|350x350px|An area chart showing the representation of different families of microprocessors in the TOP500 supercomputer ranking list, from 1992 to 2014.<ref>{{cite web|url=http://www.top500.org/statistics |title=Statistics &#124; TOP500 Supercomputer Sites |publisher=Top500.org |date= |accessdate=2014-03-22}}</ref>]]

In [[supercomputer]]s tracked by [[TOP500]], the appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel (light olive with circles, and red with circles on the diagram provided in this section, respectively) to replace most RISC processor architectures previously used in such systems (including [[PA-RISC]], [[SPARC]], [[DEC Alpha|Alpha]] and others), as well as 32-bit x86 (green with dots and purple with dots on the diagram), even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the [[Itanium]] processor.

{{As of|2014}}, the main non-x86 CPU architecture which is still used in supercomputing is the [[Power Architecture]] used by [[IBM POWER microprocessors]] (blue with a diamond pattern on the diagram), with SPARC being far behind in numbers on TOP500, while recently a [[Fujitsu]] [[SPARC64 VIIIfx]] based supercomputer without co-processors reached number one that is still in the top ten. Non-CPU architecture co-processors ([[General-purpose computing on graphics processing units|GPGPU]]) have also played a big role in performance. Intel's [[Xeon Phi]] coprocessors, which implement a subset of x86-64 with some vector extensions,<ref>{{cite web|url=https://software.intel.com/sites/default/files/forum/278102/327364001en.pdf|title=Intel® Xeon PhiTM Coprocessor Instruction Set Architecture Reference Manual|at=section B.2 Intel Xeon Phi coprocessor 64 bit Mode Limitations|publisher=Intel|date=September 7, 2012}}</ref> are also used, along with x86-64 processors, in the [[Tianhe-2]] supercomputer.<ref>{{cite web|url=http://newsroom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-computing-technologies|title=Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies|accessdate=June 21, 2013}}</ref>

== Operating system compatibility and characteristics ==
The following operating systems and releases support the x86-64 architecture in [[long mode]].

=== BSD ===

==== DragonFly BSD ====
Preliminary infrastructure work was started in February 2004 for a x86-64 port.<ref name=dfly-amd64-prelim>{{cite web |url= http://leaf.dragonflybsd.org/mailarchive/commits/2004-02/msg00011.html |title= cvs commit: src/sys/amd64/amd64 genassym.c src/sys/amd64/include asm.h atomic.h bootinfo.h coredump.h cpufunc.h elf.h endian.h exec.h float.h fpu.h frame.h globaldata.h ieeefp.h limits.h lock.h md_var.h param.h pcb.h pcb_ext.h pmap.h proc.h profile.h psl.h ... |accessdate= 2009-05-03}}</ref> This development later stalled. Development started again during July 2007<ref name=dfly-amd64-noah>{{cite web |url= http://leaf.dragonflybsd.org/mailarchive/users/2007-07/msg00016.html |title= AMD64 port |accessdate= 2009-05-03}}</ref>
and continued during [[Google Summer of Code]] 2008 and SoC 2009.<ref name=dfly-amd64-soc2008>{{cite web |url= http://www.dragonflybsd.org/docs/developer/GoogleSoC2008/ |title= DragonFlyBSD: GoogleSoC2008 |accessdate= 2009-05-03}}</ref><ref name=dfly-amd64-soc2009>{{cite web |url= http://leaf.dragonflybsd.org/mailarchive/users/2009-04/msg00091.html |title= Summer of Code accepted students |accessdate= 2009-05-03}}</ref> The first official release to contain x86-64 support was version 2.4.<ref name=dflyamd64-release>{{cite web |url= http://www.dragonflybsd.org/release24/ |title= DragonFlyBSD: release24 |accessdate= 2009-05-03}}</ref>

==== FreeBSD ====
[[FreeBSD]] first added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier&nbsp;1 platform. The 6.0-RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on the x86 architecture. Work is currently being done to integrate more fully the x86 [[application binary interface]] (ABI), in the same manner as the Linux 32-bit ABI compatibility currently works.

==== NetBSD ====
x86-64 architecture support was first committed to the [[NetBSD]] source tree on June 19, 2001. As of NetBSD&nbsp;2.0, released on December 9, 2004, ''NetBSD/amd64'' is a fully integrated and supported port.
32-bit code is still supported in 64-bit mode, with a netbsd-32 kernel compatibility layer for 32-bit syscalls. The NX bit is used to provide non-executable stack and heap with per-page granularity (segment granularity being used on 32-bit x86).

==== OpenBSD ====
[[OpenBSD]] has supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in-tree implementation of AMD64 support was achieved prior to the hardware's initial release because AMD had loaned several machines for the project's [[hackathon]] that year. OpenBSD developers have taken to the platform because of its support for the [[NX bit]], which allowed for an easy implementation of the [[W^X]] feature.

The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned use of the AMD64 extensions, but since Intel left out the page table NX bit in early Intel 64 processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX bit under the name "XD bit". [[Symmetric multiprocessing]] (SMP) works on OpenBSD's AMD64 port, starting with release 3.6 on November 1, 2004.

=== DOS ===
It is possible to enter [[long mode]] under [[DOS]] without a DOS extender,<ref>[http://www.turboirc.com/asm Tutorial for entering protected and long mode from DOS]</ref> but the user must return to real mode in order to call BIOS or DOS interrupts.

It may also be possible to enter [[long mode]] with a [[DOS extender]] similar to [[DOS/4GW]], but more complex since x86-64 lacks [[virtual 8086 mode]]. DOS itself is not aware of that, and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.

=== Linux ===
{{See also|Comparison of Linux distributions#Instruction set architecture support}}

[[Linux]] was the first operating system kernel to run the x86-64 architecture in [[long mode]], starting with the 2.4 version in 2001 (preceding the hardware's availability).<ref>{{cite web |title=Porting Linux to x86-64 |author=Andi Kleen |url=http://www.x86-64.org/pipermail/announce/2001-June/000020.html |date=2001-06-26 |quote=Status: The kernel, compiler, tool chain work. The kernel boots and work on simulator and is used for porting of userland and running programs |deadurl=yes |archiveurl=https://web.archive.org/web/20100910014057/http://www.x86-64.org/pipermail/announce/2001-June/000020.html |archivedate=September 10, 2010 |df=mdy }}</ref><ref>{{cite web |url= http://www.halobates.de/ |title= Andi Kleen's Page |author= Andi Kleen |quote= This was the original paper describing the Linux x86-64 kernel port back when x86-64 was only available on simulators.}}</ref> Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Several Linux distributions currently ship with x86-64-native kernels and [[userland (computing)|userlands]]. Some, such as [[Arch Linux]],<ref>{{cite web |url= https://wiki.archlinux.org/index.php/Arch64_FAQ |title= Arch64 FAQ |date= 2012-04-23 |quote= You can either use the multilib packages or a i686 chroot.}}</ref> [[SUSE Linux|SUSE]], [[Mandriva Linux|Mandriva]], and [[Debian]] allow users to install a set of 32-bit components and libraries when installing off a 64-bit DVD, thus allowing most existing 32-bit applications to run alongside the 64-bit OS. Other distributions, such as [[Fedora (operating system)|Fedora]], [[Slackware]] and [[Ubuntu (operating system)|Ubuntu]], are available in one version compiled for a 32-bit architecture and another compiled for a 64-bit architecture. Fedora and [[Red Hat Enterprise Linux]] allow concurrent installation of all userland components in both 32 and 64-bit versions on a 64-bit system.

[[x32 ABI]] (Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the x32 ABI to run in the 64-bit mode of x86-64 while only using 32-bit pointers and data fields.<ref name="x32ABIHOnline">{{cite news
 |url = http://www.h-online.com/open/features/Kernel-Log-x32-ABI-gets-around-64-bit-drawbacks-1342061.html
 |archiveurl = https://web.archive.org/web/20111028081253/http://www.h-online.com/open/features/Kernel-Log-x32-ABI-gets-around-64-bit-drawbacks-1342061.html
 |archivedate = October 28, 2011
 |title = Kernel Log: x32 ABI gets around 64-bit drawbacks
 |publisher = www.h-online.com
 |author = Thorsten Leemhuis
 |date = 2011-09-13
 |accessdate = 2011-11-01
 |deadurl = yes
 |df = mdy-all
 }}</ref><ref name="x32ABILinuxPlumbers">{{cite news
 |url       = http://linuxplumbersconf.org/2011/ocw/sessions/531
 |title     = x32 – a native 32-bit ABI for x86-64
 |publisher = linuxplumbersconf.org
 |accessdate= 2011-11-01}}</ref><ref name="x32ABIDevelopmentGroup">{{cite news
 |url       = http://sites.google.com/site/x32abi/
 |title     = x32-abi
 |publisher = Google Sites
 |accessdate= 2011-11-01}}</ref>
Though this limits the program to a virtual address space of 4&nbsp;GB it also decreases the memory footprint of the program and in some cases can allow it to run faster.<ref name="x32ABIHOnline"/><ref name="x32ABILinuxPlumbers"/><ref name="x32ABIDevelopmentGroup"/>

64-bit Linux allows up to 128&nbsp;[[Terabyte|TB]] of virtual address space for individual processes, and can address approximately 64&nbsp;TB of physical memory, subject to processor and system limitations.<ref name="DebianAMD64">{{cite news
 |url       = http://www.debian.org/ports/amd64/
 |title     = AMD64 Port
 |publisher = debian.org
 |accessdate= 2011-10-29}}</ref>

=== macOS ===
Mac OS X 10.4.7 and higher versions of [[Mac OS X Tiger|Mac OS X 10.4]] run 64-bit command-line tools using the POSIX and math libraries on 64-bit Intel-based machines, just as all versions of Mac OS X 10.4 and 10.5 run them on 64-bit PowerPC machines. No other libraries or frameworks work with 64-bit applications in Mac OS X 10.4.<ref>{{cite web
 |url        = https://developer.apple.com/releasenotes/DeveloperTools/RN-CompilerTools/index.html
 |archiveurl = https://web.archive.org/web/20090422045532/http://developer.apple.com/releasenotes/DeveloperTools/RN-CompilerTools/index.html
 |archivedate= 2009-04-22
 |title      = Apple – Mac OS X Xcode 2.4 Release Notes: Compiler Tools
 |publisher  = [[Apple Inc.]]
 |date       = 2007-04-11
 |accessdate = 2012-11-19}}</ref>
The kernel, and all kernel extensions, are 32-bit only.

[[Mac OS X Leopard|Mac OS X 10.5]] supports 64-bit GUI applications using [[Cocoa (API)|Cocoa]], [[Quartz (graphics layer)|Quartz]], [[OpenGL]], and [[X11]] on 64-bit Intel-based machines, as well as on 64-bit [[PowerPC]] machines.<ref>{{cite web
 |url        = https://www.apple.com/macosx/technology/64bit.html
 |archiveurl = https://web.archive.org/web/20090112055017/http://www.apple.com/macosx/technology/64bit.html
 |archivedate= 2009-01-12
 |title      = Apple – Mac OS X Leopard – Technology – 64-bit
 |publisher  = Apple Inc.
 |accessdate = 2012-11-19}}</ref>
All non-GUI libraries and frameworks also support 64-bit applications on those platforms. The kernel, and all kernel extensions, are 32-bit only.

[[Mac OS X Snow Leopard|Mac OS X 10.6]] is the first version of [[macOS]] that supports a 64-bit [[Kernel (computing)|kernel]]. However, not all 64-bit computers can run the 64-bit kernel, and not all 64-bit computers that can run the 64-bit kernel will do so by default.<ref>{{cite web
 |title      = Mac OS X v10.6: Macs that use the 64-bit kernel
 |url        = http://support.apple.com/kb/HT3770
 |publisher  = Apple Inc.
 |accessdate = 2012-11-29}}</ref>
The 64-bit kernel, like the 32-bit kernel, supports 32-bit applications; both kernels also support 64-bit applications. 32-bit applications have a virtual address space limit of 4&nbsp;GB under either kernel.<ref name="arstechnicaMacOSX64bit">{{cite web
 |url        = https://arstechnica.com/apple/reviews/2009/08/mac-os-x-10-6.ars/5
 |title      = Mac OS X 10.6 Snow Leopard: the Ars Technica review
 |publisher  = Ars Technica LLC
 |author     = John Siracusa
 |accessdate = 2010-06-20}}</ref><ref name="Apple64Bit">{{cite web
 |url        = https://www.apple.com/macosx/technology/#sixtyfourbit
 |archiveurl = https://web.archive.org/web/20110328170107/http://www.apple.com/macosx/technology/#sixtyfourbit
 |archivedate= 2011-03-28
 |title      = Mac OS X Technology
 |publisher  = Apple Inc.
 |accessdate = 2012-11-19}}</ref>

[[OS X Mountain Lion|OS X 10.8]] includes only the 64-bit kernel, but continues to support 32-bit applications.

The 64-bit kernel does not support 32-bit [[loadable kernel module|kernel extensions]], and the 32-bit kernel does not support 64-bit kernel extensions.

macOS uses the [[universal binary]] format to package 32- and 64-bit versions of application and library code into a single file; the most appropriate version is automatically selected at load time. In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel extensions that support both 32-bit and 64-bit kernels.

=== Solaris ===
{{see also|illumos}}
[[Solaris (operating system)|Solaris]] 10 and later releases support the x86-64 architecture.

For Solaris 10, just as with the [[SPARC]] architecture, there is only one operating system image, which contains a 32-bit kernel and a 64-bit kernel; this is labeled as the "x64/x86" DVD-ROM image. The default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables will run. The <code>isainfo</code> command can be used to determine if a system is running a 64-bit kernel.

For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit kernel supports both 32- and 64-bit executables, libraries, and system calls.

=== Windows ===
x64 editions of Microsoft Windows client and server—[[Windows XP Professional x64 Edition]] and [[Windows Server 2003]] x64 Edition—were released in March 2005.<ref>{{Cite web|url=http://news.microsoft.com/2005/04/25/microsoft-raises-the-speed-limit-with-the-availability-of-64-bit-editions-of-windows-server-2003-and-windows-xp-professional/#sm.0000kw91cdgntf2kwp82ed9a9yn4e|title=Microsoft Raises the Speed Limit with the Availability of 64-Bit Editions of Windows Server 2003 and Windows XP Professional {{!}} News Center|website=news.microsoft.com|access-date=2016-08-14}}</ref> Internally they are actually the same build (5.2.3790.1830 SP1),<ref>{{Cite web|url=https://support.microsoft.com/en-gb/kb/888733|title=A description of the x64-based versions of Windows Server 2003 and of Windows XP Professional x64 Edition|last=|first=|date=|website=Microsoft Support|publisher=|access-date=2016-08-14}}</ref><ref>{{Cite web|url=https://www.microsoft.com/en-us/download/details.aspx?id=3725|title=Windows Server 2003 SP1 Administration Tools Pack|website=Microsoft Download Center|access-date=2016-08-14}}</ref> as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86. [[Windows Vista]], which also has many different editions, was released in January 2007. [[Windows&nbsp;7]] was released in July 2009. [[Windows Server 2008 R2]] was sold in only x64 and Itanium editions; later versions of Windows Server only offer an x64 edition.

Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the following:
* 8&nbsp;TB of virtual address space per process, accessible from both user mode and kernel mode, referred to as the user mode address space. An x64 program can use all of this, subject to backing store limits on the system, and provided it is linked with the "large address aware" option.<ref name="VSdocLAA">{{cite web
 |url        = http://msdn.microsoft.com/en-us/library/wz223b1z(VS.80).aspx
 |title      = /LARGEADDRESSAWARE (Handle Large Addresses)
 |quote      = The /LARGEADDRESSAWARE option tells the linker that the application can handle addresses larger than 2&nbsp;gigabytes.
 |work       = Visual Studio 2005 Documentation – Visual C++ – Linker Options
 |publisher  = Microsoft
 |accessdate = 2010-06-19
}}</ref> This is a 4096-fold increase over the default 2&nbsp;GB user-mode virtual address space offered by 32-bit Windows.<ref name="Pietrek64BitWindowsProgramming">{{cite web
 |url        = http://msdn.microsoft.com/en-us/magazine/cc300794.aspx
 |title      = Everything You Need To Know To Start Programming 64-Bit Windows Systems
 |publisher  = Microsoft
 |author     = Matt Pietrek
 |date       = May 2006
 |accessdate = 2010-05-24
}}</ref><ref name="MicrosoftMoveTox64">{{cite web
 |url        = https://technet.microsoft.com/en-us/magazine/2006.01.insidemscom.aspx
 |title      = Making the Move to x64
 |publisher  = Microsoft
 |author     = Chris St. Amand
 |date       = January 2006
 |accessdate = 2010-05-24
}}</ref>
* 8&nbsp;TB of kernel mode virtual address space for the operating system.<ref name="Pietrek64BitWindowsProgramming"/> As with the user mode address space, this is a 4096-fold increase over 32-bit Windows versions. The increased space primarily benefits the file system cache and kernel mode "heaps" (non-paged pool and paged pool). Windows only uses a total of 16&nbsp;TB out of the 256&nbsp;TB implemented by the processors because early AMD64 processors lacked a <code>CMPXCHG16B</code> instruction.<ref>{{cite web
 |title      = Behind Windows x86-64’s 44-bit Virtual Memory Addressing Limit
 |url        = http://www.alex-ionescu.com/?p=50
 |accessdate = 2009-07-02
}}</ref>

Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual address spaces have been extended to 128&nbsp;TB.<ref name="win-lim-msdn"/> These versions of Windows will not install on processors that lack the <code>CMPXCHG16B</code> instruction.

The following additional characteristics apply to all x64 versions of Windows:

* Ability to run existing 32-bit applications (<code>.exe</code> programs) and dynamic link libraries (<tt>.dll</tt>s) using [[WoW64]] if WoW64 is supported on that version. Furthermore, a 32-bit program, if it was linked with the "large address aware" option,<ref name="VSdocLAA"/> can use up to 4&nbsp;GB of virtual address space in 64-bit Windows, instead of the default 2&nbsp;GB (optional 3&nbsp;GB with <tt>/3GB</tt> boot option and "large address aware" link option) offered by 32-bit Windows.<ref name="64-bitProgrammingGameDevelopers">{{cite web
 |url       = http://msdn.microsoft.com/en-us/library/ee418798(VS.85).aspx#Porting_to_64bit
 |title     = 64-bit programming for Game Developers
 |accessdate= August 21, 2013
}}</ref> Unlike the use of the <tt>/3GB</tt> boot option on x86, this does not reduce the kernel mode virtual address space available to the operating system. 32-bit applications can therefore benefit from running on x64 Windows even if they are not recompiled for x86-64.
* Both 32- and 64-bit applications, if not linked with "large address aware," are limited to 2&nbsp;GB of virtual address space.
* Ability to use up to 128&nbsp;GB (Windows XP/Vista), 192&nbsp;GB (Windows&nbsp;7), 512&nbsp;GB (Windows&nbsp;8), 1&nbsp;TB (Windows Server 2003), 2&nbsp;TB (Windows Server 2008/Windows 10), 4&nbsp;TB (Windows Server 2012), or 24&nbsp;TB (Windows Server 2016) of physical random access memory (RAM).<ref>{{cite web
 |url        = http://msdn.microsoft.com/en-us/library/aa366778(VS.85).aspx
 |title      = Memory Limits for Windows Releases
 |publisher  = Microsoft
 |accessdate = February 20, 2013}}</ref>
* [[LLP64]] data model: "int" and "long" types are 32&nbsp;bits wide, long long is 64&nbsp;bits, while pointers and types derived from pointers are 64&nbsp;bits wide.
* Kernel mode device drivers must be 64-bit versions; there is no way to run 32-bit kernel mode executables within the 64-bit operating system. User mode device drivers can be either 32-bit or 64-bit.
* 16-bit Windows (Win16) and DOS applications will not run on x86-64 versions of Windows due to removal of the [[virtual DOS machine]] subsystem (NTVDM) which relied upon the ability to use virtual 8086 mode. Virtual 8086 mode cannot be entered while running in long mode.
* Full implementation of the [[NX bit|NX]] (No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.
* Instead of FS segment descriptor on x86 versions of the [[Windows NT]] family, GS segment descriptor is used to point to two operating system defined structures: Thread Information Block (NT_TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for example, in user mode <tt>GS:0</tt> is the address of the first member of the Thread Information Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode — even though segmented addressing ''per se'' is not really used by any modern operating system.<ref name="Pietrek64BitWindowsProgramming" />
* Early reports claimed that the operating system scheduler would not save and restore the x87 FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel mode-only threads (a limitation that exists in the 32-bit version as well). The most recent documentation available from Microsoft states that the x87/MMX/3DNow! instructions may be used in long mode, but that they are deprecated and may cause compatibility problems in the future.<ref name="64-bitProgrammingGameDevelopers"/>
<!--- is there a way to use quotes with named refs?
 |quote=The x87, MMX, and 3DNow! instruction sets are deprecated in 64-bit modes.--->
* Some components like [[Microsoft Jet Database Engine]] and [[Data Access Objects]] will not be ported to 64-bit architectures such as x86-64 and IA-64.<ref>[http://msdn2.microsoft.com/en-us/library/aa384190.aspx Microsoft Developer Network – General Porting Guidelines (64-bit Windows Programming)]</ref><ref>[http://msdn.microsoft.com/library/default.asp?url=/library/en-us/dnmdac/html/data_mdacroadmap.asp Microsoft Developer Network – Data Access Road Map]{{dead link|date=July 2016 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>
* [[Microsoft Visual Studio]] can compile [[native code|native applications]] to target either the x86-64 architecture, which can run only on 64-bit Microsoft Windows, or the [[IA-32]] architecture, which can run as a 32-bit application on 32-bit Microsoft Windows or 64-bit Microsoft Windows in [[WoW64]] emulation mode. [[Managed code|Managed applications]] can be compiled either in IA-32, x86-64 or AnyCPU modes. Software created in the first two modes behave like their IA-32 or x86-64 native code counterparts respectively; When using the AnyCPU mode however, applications in 32-bit versions of Microsoft Windows run as 32-bit applications, while they run as a 64-bit application in 64-bit editions of Microsoft Windows.

== Video game consoles ==
Both [[PlayStation 4]] and [[Xbox One]] and their successors incorporate AMD x86-64 processors, based on [[Jaguar (microarchitecture)|Jaguar]] [[microarchitecture]].<ref name=XboxOneMay2013Anandtechcomparison>{{cite news |title= The Xbox&nbsp;One: Hardware Analysis & Comparison to PlayStation&nbsp;4 |author= Anand Lal Shimpi |publisher= Anandtech |url= http://www.anandtech.com/show/6972/xbox-one-hardware-compared-to-playstation-4/2 |date= 2013-05-21 |accessdate= 2013-05-22}}</ref><ref name=XboxOneMay2013SpecGameinformer>{{cite web |url= http://www.gameinformer.com/b/news/archive/2013/05/21/the-tech-spec-test-xbox-one-vs-playstation-4.aspx |title= The Tech Spec Test: Xbox&nbsp;One Vs. PlayStation&nbsp;4 |publisher= Game Informer |date= 2013-05-21 |accessdate= 2013-05-22}}</ref> Firmware and games are written in x86-64 code;, no legacy x86 code is involved with them.

== Industry naming conventions ==
Since AMD64 and Intel 64 are substantially similar, many software and hardware products use one vendor-neutral term to indicate their compatibility with both implementations. AMD's original designation for this processor architecture, "x86-64", is still sometimes used for this purpose,<ref name="apple-x86-64"/> as is the variant "x86_64".<ref name="apple-x86_64-arch-manpage"/><ref name="apple-x86_64-email"/> Other companies, such as [[Microsoft]]<ref name="ms-x64"/> and [[Sun Microsystems]]/[[Oracle Corporation]],<ref name="solaris-x64"/> use the contraction "x64" in marketing material.

The term [[IA-64]] refers to the [[Itanium]] processor, and should not be confused with x86-64, as it is a completely different instruction set.

Many operating systems and products, especially those that introduced x86-64 support prior to Intel's entry into the market, use the term "AMD64" or "amd64" to refer to both AMD64 and Intel 64.
* '''amd64'''
** Most [[BSD]] systems such as [[FreeBSD]], [[MidnightBSD]], [[NetBSD]] and [[OpenBSD]] refer to both AMD64 and Intel 64 under the architecture name "amd64".
** Some [[Linux distribution]]s such as [[Debian]], [[Ubuntu (operating system)|Ubuntu]], and [[Gentoo Linux|Gentoo]] refer to both AMD64 and Intel 64 under the architecture name "amd64".
** [[Microsoft Windows]]'s x64 versions use the AMD64 moniker internally to designate various components which use or are compatible with this architecture. For example, the [[environment variable]] PROCESSOR_ARCHITECTURE is assigned the value "AMD64" as opposed to "x86" in 32-bit versions, and the system directory on a Windows x64 Edition installation CD-ROM is named "AMD64", in contrast to "i386" in 32-bit versions.<ref>[http://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture_fields.aspx ProcessorArchitecture Fields]</ref>
** Sun's [[Solaris (operating system)|Solaris]]' ''isalist'' command identifies both AMD64- and Intel 64-based systems as "amd64".
** [[Java Development Kit]] (JDK): the name "amd64" is used in directory names containing x86-64 files.
* '''x86_64'''
** The [[Linux kernel]]<ref>{{cite web | url = http://lxr.linux.no/#linux+v3.7.8/arch/x86/configs/x86_64_defconfig | title = An example file from Linux 3.7.8 kernel source tree displaying the usage of the term x86_64 | accessdate = 2013-02-17 | deadurl = yes | archiveurl = https://web.archive.org/web/20050923210216/http://lxr.linux.no/#linux+v3.7.8/arch/x86/configs/x86_64_defconfig | archivedate = September 23, 2005 | df = mdy-all }}</ref> and the [[GNU Compiler Collection]] refers to 64-bit architecture as "x86_64".
** Some Linux distributions, such as [[Fedora (operating system)|Fedora]], [[openSUSE]], and [[Arch Linux]] refer to this 64-bit architecture as "x86_64".
** Apple [[macOS]] refers to 64-bit architecture as "x86-64" or "x86_64", as seen in the Terminal command <code>arch</code><ref name="apple-x86_64-arch-manpage"/> and in their developer documentation.<ref name="apple-x86-64"/><ref name="apple-x86_64-email"/>
** Breaking with most other BSD systems, [[DragonFly BSD]] refers to 64-bit architecture as "x86_64".
** [[Haiku (operating system)|Haiku]] refers to 64-bit architecture as "x86_64".

== Licensing ==
x86-64/AMD64 was solely developed by AMD. AMD holds patents on techniques used in AMD64;<ref>{{patent|US|6877084}}</ref><ref>{{patent|US|6889312}}</ref><ref>{{patent|US|6732258}}</ref> those patents must be licensed from AMD in order to implement AMD64. Intel entered into a cross-licensing agreement with AMD, licensing to AMD their patents on existing x86 techniques, and licensing from AMD their patents on techniques used in x86-64.<ref>{{cite web
 |url=http://contracts.corporate.findlaw.com/agreements/amd/intel.license.2001.01.01.html 
 |title=Patent Cross License Agreement Between AMD and Intel 
 |accessdate=2009-08-23 
 |date=2001-01-01 
 |deadurl=yes 
 |archiveurl=https://web.archive.org/web/20070621084244/http://contracts.corporate.findlaw.com/agreements/amd/intel.license.2001.01.01.html 
 |archivedate=June 21, 2007 
}}</ref> In 2009, AMD and Intel settled several lawsuits and cross-licensing disagreements, extending their cross-licensing agreements.<ref>{{cite web |url = https://www.sec.gov/Archives/edgar/data/2488/000119312509236705/dex101.htm |title = AMD Intel Settlement Agreement}}</ref><ref>{{cite web |url= http://news.cnet.com/8301-1001_3-10396188-92.html |publisher= CNET |author= Stephen Shankland and Jonathan E. Skillings |title= Intel to pay AMD $1.25 billion in antitrust settlement |date= 2009-11-12 |accessdate= 2012-04-24}}</ref><ref>{{cite web|last1=Smith|first1=Ryan|title=AMD and Intel Settle Their Differences: AMD Gets To Go Fabless|url=http://www.anandtech.com/show/2873|website=AnandTech|archiveurl=https://web.archive.org/web/20100513042947/http://www.anandtech.com/show/2873|archivedate=13 May 2010|date=12 November 2009}}</ref>

== See also ==
* [[AMD Generic Encapsulated Software Architecture]] (AGESA)
* [[X32 ABI]]

==Notes ==
{{reflist|group=note}}

== References==
{{reflist|30em}}

== External links ==
* [http://developer.amd.com/resources/documentation-articles/developer-guides-manuals AMD's AMD64 Developer Guides and Manuals]
* [http://www.stanford.edu/class/ee380/Abstracts/O00927.html x86-64: Extending the x86 architecture to 64-bits] – technical talk by the architect of AMD64 ([https://web.archive.org/web/20100813052749/http://stanford-online.stanford.edu/courses/ee380/000927-ee380-100.asx video archive]), and [http://www.stanford.edu/class/ee380/Abstracts/040107.html second talk by the same speaker] ([https://web.archive.org/web/20100813100133/http://stanford-online.stanford.edu/courses/ee380/040107-ee380-100.asx video archive])
* [http://www.xbitlabs.com/news/other/display/20041227094638.html AMD's "Enhanced Virus Protection"]
* [https://www.theregister.co.uk/2005/08/23/intel_fixes_em64t/ Intel tweaks EM64T for full AMD64 compatibility]
* [http://www.extremetech.com/extreme/56018-analyst-intel-reverseengineered-amd64 Analyst: Intel Reverse-Engineered AMD64]
* [http://marc.info/?l=linux-kernel&m=107766481408468&w=2 Early report of differences between Intel IA32e and AMD64]
* [ftp://gcc.gnu.org/pub/gcc/summit/2003/Porting%20to%2064%20bit.pdf Porting to 64-bit GNU/Linux Systems], by Andreas Jaeger from [[GCC Summit]] 2003. An excellent paper explaining almost all practical aspects for a transition from 32-bit to 64-bit.
* [http://techreport.com/reviews/2005q1/64-bits/index.x?pg=1 Tech Report article: 64-bit computing in theory and practice]
* [http://www.intel.com/technology/intel64/index.htm Intel 64 Architecture]
* [https://web.archive.org/web/20110403005033/http://software.intel.com/en-us/articles/all-about-64-bits/ Intel Software Network: "64 bits"]
* [http://www.turboirc.com/asm TurboIRC.COM tutorial of entering the protected and the long mode the raw way from DOS]
* [https://web.archive.org/web/20100123010204/http://software.intel.com/en-us/articles/seven-steps-of-migrating-a-program-to-a-64-bit-system/ Seven Steps of Migrating a Program to a 64-bit System]
* [http://msdn.microsoft.com/en-us/library/aa366778%28VS.85%29.aspx Memory Limits for Windows Releases]

<!-- [[Category:Advanced Micro Devices products]] category is added to the AMD64 redirect page instead of here, in order to make that name appear in the category listing rather than "X86-64"; -->
[[Category:Computer-related introductions in 2003]]
[[Category:X86 architecture]]